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2024 Research Needs Document: Packaging / Packaging CHIRP
Semiconductor Research Corp. (SRC)
Research Triangle Park, NC 27703



Table 1.1 list such topics with the expectation that proponents will address corresponding challenges in those areas and articulate how their proposed research may advance the state of the art in terms of quantitative holistic critical metric goals for the proposed project(s). The proposals should include justifications and benchmarks of the proposed approaches based on theoretical, modeling, and or experimental evidence. Researchers are encouraged to refer to the sections of the MAPT Roadmap listed in Table 1.1 to understand the relevance of the research topic to industry. Proposals on other research topics beyond those listed in Table 1.1 but addressing challenges identified in the MAPT roadmap and in Table 1.2 are also considered as part of this solicitation.

Table 1.1, Specific Topics from the MAPT Roadmap

Design Enablement and Tools

MAPT, 10'23, Section 7.2, “Chip Packaging Architectures and Codesign”

MAPT, 10’23, Section 7.8, “Performance and Process Modeling and Model Validation”

Interconnects, including photonics

MAPT, 10’23, Section 7.3, “Next generation interconnects”

MAPT, 10’23, Section 7.5, “Materials”

MAPT, 10’23, Section 7.6, “Substrates”

MAPT, 10'23, Section 7.7, “Assembly and Test”

MAPT, 10’23, Section 7.9, “Reliability”

MAPT, 10’23, Section 8.1, “Introduction”

Power Delivery and Thermal Management

MAPT, 10’23, Section 7.4, “Power Delivery and Thermal Management”

MAPT, 10'23, Table 7.2, “High Frequency Inductors (100MHz) on Package”

MAPT, 10'23, Table 7.2, “EDA tools to run 3DIC simulations for >3die stacks”

MAPT, 10’23, Section 7.4, “Thermal optimization across the package scale and system scale”

MAPT, 10’23, Table 7.3, “Thermal Management requirements”

MAPT, 10’23, Table 7.5, “Integrated Voltage Regulator chip embedding”

Metrology, Modeling, and Test

MAPT, 10’23, Section 7.8,  “Performance and Process Modeling and Model Validation”

MAPT, 10’23, Section 8.6, “Challenges, Future Needs, and Possible Solutions”

MAPT, 10’23, Section 10.3, “Metrology for Devices”

MAPT, 10’23, Section 10.4, “Metrology for Packaging and Highly Integrated Systems”

MAPT, 10’23, Section 10.5, “Acceleration of Metrology through Big Data, Machine Learning, AI, and Hybrid Metrology”

MAPT, 10’23, Section 10.6, “State of the Art / Product Example”

MAPT, 10’23, Section 10.8, “Challenges, Future Needs, and Possible Solutions”

Materials including Solder and Wire-bonds

MAPT, 10’23, Section 2.3, “Environmental Sustainability: Product Design, Development, Manufacturing, and End-of-Life Management”

MAPT, 10’23, Section 5.3, “Power Management, Power Distribution, and Power Electronic”

MAPT, 10’23, Section 5.4, “RF to THz Devices, Circuits, and Systems”

MAPT, 10’23, Section 6.5, “New Materials and Processes for Photonics and MEMS”

MAPT, 10’23, Section 7.5, “Materials”

MAPT, 10’23, Section 7.6, “Substrates”

MAPT, 10’23, Table 7.4, “Warpage management”

MAPT, 10’23, Section 8.1, “Introduction”

MAPT, 10’23, Section 8.2, “Material Requirements for Power Electronics/ Electrification Advanced Packaging”

MAPT, 10’23, Section 8.3, “Material Requirements for Sub-THz mmWave Packaging (5G/6G and Automotive Sensing”

MAPT, 10’23, Section 8.4 “Material Requirements for High-performance Compute Packaging”

MAPT, 10’23, Section 8.6, “Challenges, Future Needs, and Possible Solutions”

Table 1.2, Add-on Topics Not Listed in MAPT Roadmap

Interconnects, including photonics

  • Innovative, low-cost packaging for System-in-Package (SiP)

Power Delivery and Thermal Management

  • Small die cooling
  • Thermal management of ultra-fast on-die transients

Metrology, Modeling, and Test

  • Models of materials and interfaces, especially predictive modeling for reliability failures
  • Predictive modeling methodology development for package interfaces

Materials including Solder and Wire-bonds

  • Materials for lower-cost lead frame packages, including QFP and QFN packages
  • Materials for advanced wire-bonded packages, including stacked die, high power, higher functionality, high voltage isolation, and high comparative tracking index (CTI) epoxy mold compounds
  • Materials suitable for high temperature applications, (Tamb ≥ 180°C and Tj ≥ 200°C), which can pass AEC Grade 0 conditions
  • Encapsulation /coating materials )materials (e.g molding compounds)- High interface reliability  High adhesion strengths to semiconductor, dielectric, metal, and polymer interfaces (Si die, Cu bump, solder bump, lead frames, and organic packages
  • Battery management especially for EV and other packages (this can be part of  Design enablement or Interconnect)
  • EMI Shielding
  • High-efficiency, high-density, cost-effective inductors: Soft magnetic materials with resistivity > 1 mΩ·cm, high anisotropy field, and low coercivity while offering a high saturation magnetic flux density Bsat > 2 T, and that maintain permeability at frequencies up to 1 GHz

Direct links to the chapters in MAPT Roadmap:
Chapter 2: https://srcmapt.org/chapter2/
Chapter 5: https://srcmapt.org/chapter5/
Chapter 6: https://srcmapt.org/chapter6/
Chapter 7: https://srcmapt.org/chapter7/
Chapter 8: https://srcmapt.org/chapter8/
Chapter 10: https://srcmapt.org/chapter10/


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